| Part Number | ZL30265 |
| Manufacturer | Microchip |
| Title | Any-to-Any Clock Multiplier and Frequency Synthesizer |
| Description | 8 5. FUNCTIONAL DESCRIP... |
| Features |
• Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register Register Map: Sec... |
| File Size | 2.25MB |
| Datasheet |
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ZL30260 : 7 5. FUNCTIONAL DESCRIPTION ... 9 5.1 DEVICE IDENTIFICATION.9 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ... 9 5.2.1 ZL30260 and ZL30262—Internal ROM, External or No EEPROM 10 5.2.2 .
ZL30260 : Register Map: Section 6.2 Features • Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • High-resolution frac-N APLL with 0ppm error • The APLL has a fractional divider and an integer divider to make two independent frequency families • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Output jitter from fractional dividers is typically 1ps RM.
ZL30261 : 7 5. FUNCTIONAL DESCRIPTION ... 9 5.1 DEVICE IDENTIFICATION.9 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ... 9 5.2.1 ZL30260 and ZL30262—Internal ROM, External or No EEPROM 10 5.2.2 .
ZL30261 : Register Map: Section 6.2 Features • Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • High-resolution frac-N APLL with 0ppm error • The APLL has a fractional divider and an integer divider to make two independent frequency families • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Output jitter from fractional dividers is typically 1ps RM.
ZL30262 : 7 5. FUNCTIONAL DESCRIPTION ... 9 5.1 DEVICE IDENTIFICATION.9 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ... 9 5.2.1 ZL30260 and ZL30262—Internal ROM, External or No EEPROM 10 5.2.2 .
ZL30262 : Register Map: Section 6.2 Features • Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • High-resolution frac-N APLL with 0ppm error • The APLL has a fractional divider and an integer divider to make two independent frequency families • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Output jitter from fractional dividers is typically 1ps RM.
ZL30263 : 7 5. FUNCTIONAL DESCRIPTION ... 9 5.1 DEVICE IDENTIFICATION.9 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ... 9 5.2.1 ZL30260 and ZL30262—Internal ROM, External or No EEPROM 10 5.2.2 .
ZL30263 : Register Map: Section 6.2 Features • Four Flexible Input Clocks • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • High-resolution frac-N APLL with 0ppm error • The APLL has a fractional divider and an integer divider to make two independent frequency families • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Output jitter from fractional dividers is typically 1ps RM.
ZL30264 : 8 5. FUNCTIONAL DESCRIPTION . 10 5.1 DEVICE IDENTIFICATION.....10 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET . 10 5.2.1 ZL30264 and ZL30266—Internal ROM, External or No EEPROM......
ZL30266 : 8 5. FUNCTIONAL DESCRIPTION . 10 5.1 DEVICE IDENTIFICATION.....10 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET . 10 5.2.1 ZL30264 and ZL30266—Internal ROM, External or No EEPROM......
ZL30267 : 8 5. FUNCTIONAL DESCRIPTION . 10 5.1 DEVICE IDENTIFICATION.....10 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET . 10 5.2.1 ZL30264 and ZL30266—Internal ROM, External or No EEPROM......