| Part Number | IS43DR16640B |
| Manufacturer | ISSI |
| Title | 1Gb DDR2 SDRAM |
| Description | DDR2 SDRAM (128Mx8) TW-BGA Ball-out (Top-View) (8.00mm x 10.50mm) Symbol CK, CK# CKE CS# RAS#,CAS#,WE# A[13:0] BA[2:0] DQ[7:0] DQS, DQS# RDQS, RD... |
| Features |
Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential or Interleave Pro... |
| File Size | 1.04MB |
| Datasheet |
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IS43DR16640BL : DDR2 SDRAM (128Mx8) TW-BGA Ball-out (Top-View) (8.00mm x 10.50mm) Symbol CK, CK# CKE CS# RAS#,CAS#,WE# A[13:0] BA[2:0] DQ[7:0] DQS, DQS# RDQS, RDQS# DM VDD VSS VDDQ VSSQ VREF VDDL VSSDL ODT NC Description Input clocks Clock enable Chip Select Command control pins Address Bank Address I/O Data Strobe Redundant Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect Rev. G 3/25/2015 Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS# are identical in function and timing to strobe pair DQS & DQS# and input masking fun.
IS43DR16640C : MAY 2013 ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ADDRESS TABLE Parameter Configuration Refresh Count 128M x 8 16M x 8 x 8 banks 8K/64ms 64M x 16 8M x 16 x 8 banks 8K/64ms Row Addressing 16K (A0-A13) 8K (A0-A12) Column Addressing 1K (A0-A9) Bank Addressing BA0 - BA2 1K (A0-A9) BA0 - BA2 Precharge Addressing A10 A10 OPTIONS • Configuration(s): 128Mx8 (16Mx8x8 banks): IS43/46DR81280C 64Mx16 (8Mx16x8 banks): IS43/46DR16640C • Package: x8: 60-ball BGA (8mm x 10.