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Part Number
|
M13S128324A |
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Manufacturer
|
ESMT |
|
Title
|
Double Data Rate SDRAM |
|
Description
|
Pin Name
Function
Pin Name
Function
A0~A11, BA0,BA1
Address inputs - Row address A0~A11 - Colu...
|
|
Features
|
Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential cl...
|
|
Published
|
Apr 3, 2024 |
|
Datasheet
|
M13S128324A PDF File
|
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2, 2.5, 3
...
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