A63L73321 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Preliminary Document Title 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History Rev.
No.
0.
0 0.
1 0.
2 0.
3 0.
4 History Initial issue Change fast access times from 8.
5/9.
5/10 ns to 9.
5/10/12 ns Change ICC1 from 300mA to 350mA(max.
) Add description for 100/91/83 MHz Add description for 2E1D at page 1 Modify waveform at page 11 Delete -9.
5 & -10 part number Change -12 cycle time from 12ns to 15ns Issue Date December 14, 1998 June 9, 1999 December 19, 1999 June 20, 2000 August 29, 2001 Remark Preliminary PRELIMINARY (August, 2000, Version 0...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)