1CY 626 4 PRELIMINARY CY6264 8K x 8 Static RAM Features • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected over 70% when deselected.
The CY6264 is packaged in a 450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the writing/reading operation of the memory.
When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12).
Reading the device is accomplished by selecting the device...

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