FIN1026 3.
3V LVDS 2-Bit High Speed Differential Receiver June 2002 Revised June 2002 FIN1026 3.
3V LVDS 2-Bit High Speed Differential Receiver General Description This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology.
The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even at high frequencies.
This device is ideal for high speed transfer of clock and data.
The FIN1026 can be paired with its companion driver, the FIN1025, or any other LVDS driver.
Features s Greater than 400Mbs data rate s Flow-through pinou...

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