FIN1048 3.
3V LVDS 4-Bit Flow-Through High Speed Differential Receiver September 2001 Revised August 2003 FIN1048 3.
3V LVDS 4-Bit Flow-Through High Speed Differential Receiver General Description This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology.
The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even at high frequencies.
This device is ideal for high speed transfer of clock and data.
The FIN1048 can be paired with its companion driver, the FIN1047, or any other LVDS driver.
Features s Greater than 400Mb...

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