Integrated Circuit Systems, Inc.
AV9170 Clock Synchronizer and Multiplier General Description The AV9170 generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5V VDD).
Using ICS’s proprietary phase-locked loop (PLL) analog CMOS technology, the AV9170 is useful for regenerating clocks in high speed systems where skew is a major concern.
By the use of the two select pins, multiples or divisions of the input clock can be generated with zero delay (see Tables 2 and 3).
The standard versions produce two outputs, where CLK2 is always a divide by two version of CLK1.
The AV9170 is also useful to recover poor duty cycle clocks.
A 50 MHz signal w...

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