74F125 Quad Buffer (3-STATE) April 1988 Revised July 1999 74F125 Quad Buffer (3-STATE) Features s High impedance base inputs for reduced loading Ordering Code: Order Number 74F125SC 74F125SJ 74F125PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.
150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.
3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide Devices also available in Tape and Reel.
Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol IEEE/IEC Connection Diagram Unit Loading/Fan Out U.
L.
Pin Names An, Bn On Description HIGH/LOW Inputs Outputs 1.
0/0.
...

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