Philips Semiconductors Product specification Dual 4-input NAND gate 74ABT20 QUICK REFERENCE DATA SYMBOL PARAMETER Propagation delay An, Bn, Cn, Dn to Yn Output to Output skew Input capacitance Total supply current VI = 0V or VCC Outputs disabled; VCC = 5.
5V CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT LOGIC DIAGRAM A0 B0 1 2 6 4 5 Y0 tPLH tPHL tOSLH tOSHL CIN ICC CL = 50pF; VCC = 5V 2.
7 2.
2 0.
3 3 50 C0 ns D0 ns pF µA VCC = Pin 14 GND = Pin 7 A1 B1 C1 D1 9 10 8 12 13 Y1 SA00352 PIN CONFIGURATION A0 B0 NC C0 D0 Y0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D1 C1 NC B1 A1 Y1 LOGIC SYMBOL (IEEE/IEC) 1 2 6 4 5 & 9 SA00350 10 8 12 13 PIN DESCRIPTION PIN NUMBER 1, 2, 4, 5, 9, 10...

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