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XCR3064XL-6VQ100C

XCR3064XL 64 Macrocell CPLD

Description

0 R XCR3064XL 64 Macrocell CPLD 0 14 DS017 (v1.6) January 8, 2002 Product Specification Features • • • • • Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages • • 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS ...


Xilinx

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