| Part Number | PXA270 |
| Manufacturer | Intel Corporation |
| Title | Electrical/ Mechanical/ and Thermal Specification |
| Description | at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde... |
| Features |
— IEEE JTAG interface with boundary scan Hardware performance-monitoring features with on-chip trace buffer Real-time clock Operating-system timers LCD Controller Universal Subscriber Identity Module interface
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Low power: — Wireless Intel Speedstep® Technology — Less than 500 mW typical ...
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| File Size | 1.53MB |
| Datasheet |
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PXA272 : Type of memory: SRAM Data bus width: 16 bits ROM/SRAM delay first access: 30* Clock pulse equivalent of processor ROM/SRAM delay next access: 30* clock pulse equivalent of processor ROM/SRAM Recovery Time Fast/Slow device: Slow Device Read Operation With an internal reference clock of 520 MHz (1.923-ns clock period), the register settings required to set up proper read operations are shown in Table 3. RDF (ROM Delay First access), which defines the number of wait states inserted in a read cycle, needs to be 30 times the REF_CLK clock cycle. This essentially extends the chip select enable duration of a read cycle to 30 x REF_CLK = 57.7ns. Figure 2 shows the timing details of a read operation.