PRELIMINARY DATA SHEET 512M bits DDR SDRAM EDD5104ABTA (128M words × 4 bits) EDD5108ABTA (64M words × 8 bits) Description The EDD5104AB is a 512M bits Double Data Rate (DDR) SDRAM organized as 33,554,432 words × 4 bits × 4 banks.
The EDD5108AB is a 512M bits DDR SDRAM organized as 16,777,216 words × 8 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
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