MC10E155, MC100E155 5V ECL 6−Bit 2:1 Mux−Latch Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs.
When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL.
A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs.
The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
Features • 850 ps Max.
LEN to Output • 825 ps Max.
D to Output • Single−Ended Outputs • Asynchronous Master Reset • Dual Latch−Enables • PECL Mode Operating Range: VCC = 4.
2 V to 5.
7 V with VEE = 0...

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