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DataSheet4U.
com MC10E167, MC100E167 5V ECL 6-Bit 2:1 MUX-Register Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs.
Input data are selected by the Select control, SEL.
The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both).
A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.
Features http://onsemi.
com • • • • • • • • • • • • • • The 100 Series contains temperature compensation.
1000 MHz Min.
Operating Frequency 800 ps Max.
Clock to Output Single-Ended Outputs Asynchronous Master Resets Dual Clocks PECL Mode Operating Range: VCC = 4.
2 V to 5.
7 V wit...

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