SDRAM (Rev.
0.
3) MITSUBISHI LSIs Feb ‘97 Preliminary M5M4V4S40CTP-12, -15 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM PRELIMINARY Some of contents are described for general products and are subject to change without notice.
DESCRIPTION The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit Synchronous DRAM, with LVTTL interface.
All inputs and outputs are referenced to the rising edge of CLK.
The M5M4V4S40CTP achieves very high speed data rates up to 83MHz, and is suitable for main memory or graphic memory in computer systems.
Vdd DQ0 DQ1 VssQ DQ2 DQ3 VddQ DQ4 DQ5 VssQ DQ6 DQ7 VddQ DQML /WE /CAS /RAS /CS BA A8 A0 A1 A2 A3 Vdd PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 ...

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