MITSUBISHI DIGITAL ASSP M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PIN CONFIGURATION (TOP VIEW) 2 D4 1 D5 32 D6 31 D7 30 D8 29 RS 28 WEN1 27 WCLK 26 WEN2/LD 25 VCC 24 Q8 23 Q7 22 Q6 21 Q5 4 D2 3 D3 DESCRIPTION M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology.
These FIFOs are applicable for a data buffer as networks and communications.
The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1,WEN2).
Data present at the data input pins(D0-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writ...

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