M68AF127B 1Mbit (128K x8), 5V Asynchronous SRAM FEATURES SUMMARY s SUPPLY VOLTAGE: 4.
5 to 5.
5V s s s s s s Figure 1.
Packages 128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER SO32 (MC) 32 1 PDIP32 (B) TSOP32 (NK) 8 x 13.
4 mm TSOP32 (N) 8 x 20 mm August 2003 1/21 M68AF127B TABLE OF CONTENTS SUMMARY DESCRIPTION .
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3 Figure 2.
Logic Diagram .
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