MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16).
Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length.
DMA transfer rate of up to 13.
3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK.
Complete Level 2 implementation compatible with X.
25 LAPB, ISDN LAPD, X.
32, and X.
75 Protocols.
Handles all error recovery, sequencing, and S and U frame control.
Pin-for-pin and architecturally compatible with MK5025 (X.
25/LAPD), MK5027 (CCS#7) and MK5029(SDLC).
Buffer Management includes: - Initi...

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