S DU/D40N03L
S amHop Microelectronics C orp.
May,2004 ver1.
1
N-C hannel Logic Level E nhancement Mode Field E ffect
Transistor
P R ODUC T S UMMAR Y
V DS S
30V
F E AT UR E S
Max
ID
42A
R DS (ON) ( m W )
S uper high dense cell design for low R DS (ON ).
10 @ V G S = 10V 16 @ V G S = 4.
5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
D G S
G D
S
G
S DU S E R IE S TO-252AA(D-P AK)
S DD S E R IE S TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (T C =25 C unless otherwise noted)
P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous -P ulsed
a
S ymbol V DS V GS @ TJ=125 C ID IDM IS PD T J , T S TG
Limit 30 20 42 105 40 50 -55 to 175
Unit V V A A A W C
...