SP504

SP5000 : .

SP50001 : China Electronics Technology Group Corporation No.26 Research Institute 500MHz Low-loss SAW Filter www.DataSheet4U.com 45MHz Bandwidth Part Number: SP50001 www.sipatsaw.com SIPAT Co., Ltd. Specifications Parameter Center Frequency Insertion Loss(f0±20MHz) 1.5 dB Bandwidth 3 dB Bandwidth 35 dB Bandwidth Passband Variation(f0±20MHz) Absolute Delay Group Delay Variation(f0±20MHz) 100～470MHz Ultimate Rejection 530～550MHz 550～1000MHz Material Temperature coefficient Ambient Temperature Package Size Unit MHz dB MHz MHz MHz dB usec Minimum 40 45 30 30 30 Typical 500 21 46.4 48.34 60.94 1.1 0.66 25 26 18 33 -47 25 SMD7.0*5.0 Maximum 24 60 1.5 150 - nsec dB dB dB KHz/°C °C Notes: 1. All spe.

SP5001 : User’s Manual IP Telephone Gateway Model No.: SP5001/S http://www.micronet.info Table of Contents 1. VOIP GATEWAY OVERVIEW ..4 1.1. OVERVIEW. 4 1.2. FEATURES . 4 1.3. DEFAULT SETTINGS 5 1.4. HARDWARE SPECI.

SP5001 : The SP5001 Series is a highly integrated Common Mode Filter (CMF) providing both ESD protection and EMI common mode noise filtering for systems using high speed differential serial interfaces, such as MIPI D-PHY or HDMI. The SP5001 Series can protect and filter two differential line pairs in a small RoHS-compliant TDFN-10 package, with cost and space savings over discrete solutions. Pinout In 1+ 1 In 1- 2 G ND 3 In 2+ 4 In 2- 5 1 0 Out 1+ 9 Out 18 G ND 7 Out 2+ 6 Out 2- Note :This drawing is not to scale. Functional Block Diagram Pin1 External Pin2 (Connector) Pin4 Pin5 Pin10 Pin9 Internal (ASIC) Pin7 Pin6 Features • Large differential bandwidth 2.5 GHz • High Common Mode Stop Band .

SP5001 : .

SP5001-04TTG : The SP5001 Series is a highly integrated Common Mode Filter (CMF) providing both ESD protection and EMI common mode noise filtering for systems using high speed differential serial interfaces, such as MIPI D-PHY or HDMI. The SP5001 Series can protect and filter two differential line pairs in a small RoHS-compliant TDFN-10 package, with cost and space savings over discrete solutions. Pinout In 1+ 1 In 1- 2 G ND 3 In 2+ 4 In 2- 5 1 0 Out 1+ 9 Out 18 G ND 7 Out 2+ 6 Out 2- Note :This drawing is not to scale. Functional Block Diagram Pin1 External Pin2 (Connector) Pin4 Pin5 Pin10 Pin9 Internal (ASIC) Pin7 Pin6 Features • Large differential bandwidth 2.5 GHz • High Common Mode Stop Band .

SP5001S : User’s Manual IP Telephone Gateway Model No.: SP5001/S http://www.micronet.info Table of Contents 1. VOIP GATEWAY OVERVIEW ..4 1.1. OVERVIEW. 4 1.2. FEATURES . 4 1.3. DEFAULT SETTINGS 5 1.4. HARDWARE SPECI.

SP5002 : The SP5002 Series is a highly integrated Common Mode Filter (CMF) providing both ESD protection and EMI common mode noise filtering for systems using high speed differential serial interfaces, such as MIPI D-PHY. The SP5002 Series can protect and filter three differential line pairs in a small RoHS-compliant TDFN-16 package, with cost and space savings over discrete solutions. Pinout I n 1+ 1 I n 1- 2 GND 3 I n 2+ 4 I n 2- 5 GND 6 I n 3+ 7 I n 3- 8 16 Out 1+ 15 Out 114 GND 13 Out 2+ 12 Out 211 GND 10 Out 3+ 9 Out 3- Note :This drawing is not to scale. Functional Block Diagram Pin1 Pin2 External Pin4 (Connector) Pin5 Pin7 Pin8 Pin16 Pin15 Pin13 Internal Pin12 (ASIC) Pin10 Pin9 Pin3, P.

SP5002 : .

SP5003 : The SP5003 Series is a highly integrated Common Mode Filter (CMF) providing both ESD protection and EMI common mode noise filtering for systems using high speed differential serial interfaces, such as MIPI D-PHY or HDMI. The SP5003 Series can protect and filter two differential line pairs in a small RoHS-compliant TDFN-10 package, with cost and space savings over discrete solutions. Pinout In 1+ 1 In 1- 2 G ND 3 In 2+ 4 In 2- 5 1 0 Out 1+ 9 Out 18 G ND 7 Out 2+ 6 Out 2- Note :This drawing is not to scale. Functional Block Diagram Pin1 External Pin2 (Connector) Pin4 Pin5 Pin10 Pin9 Internal (ASIC) Pin7 Pin6 Pin3 Pin8 Features • Large differential bandwidth 4.0 GHz • High Common Mode.

SP5005 : SP5005 SOP16 PWM PWM · · · · · · · MODSEL PWMDC CTPWM PWMOUT CLAMP LOAD ISEN 2.5V 60uA 1.0V OR TIME_P RT Low F requency PWM Generator Protection Circuit TIME_INN CLAMP TIME_INN INN CLAMP UVLO CMP 1.25V AND DELAY NOUT2 AND AND BAND GAP REF. TIME_INN TIME_P RT AND DELAY NOUT1 AND AND 1/2 Clock Ramp Wave NOT SP5005 VDD=4.5V-8.0V ON/OF F CTOSC LOAD TIMER -1- Free Datasheet http://www.0PDF.com -2- Free Datasheet http://www.0PDF.com 4.0 Vdd=8 Ta=25 1.2125 2.2 1.25 2 4.0 0.2 8 V mA V mV V V kHz V V V dB Mhz uA uA V V V mV V mV uA V V Hz V V V % Pin1 Vdd=4.0-13.2V Ta=25 1.2875 20 4.2 0.3 400 3.8 0.1 50 2.30 0.4 0.1 60 1 Pin5 0.3V Pin5 0.3V Vdd=12V Ta=25 3 80 1.5 .

SP502 : The SP502 is a highly integrated serial transceiver that allows software control of its interface modes. It offers hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS-485, V.35, and EIA-530. The SP502 is fabricated using low–power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Drivers Receivers SP502 Charge Pump Driver Decode Receiver Decode Rev. 7/21/03 SP502 Multi-Mode Serial Transceiver © Copyright 2003 Sipex Corporation 1 SPECIFICATIONS MIN. LOGIC INPUTS VIL VIH LOGIC OUTPUTS VOL VOH RS-485 DRIVER TTL Input Levels VIL VIH Outputs HIGH Level Output LOW level Output Differential Output Balance Op.

SP5024 : The SP5024 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard data, clock, enable, three-wire data bus. The data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of th.

SP5026 : The SP5026 is a programming variant of the SP5510, allowing the design of one tuner with either 12C bus or 3-wire bus format depending on which device is inserted. The SP5026, when used with a TV varicap tuner, forms a complete phase locked loop tuning system. The circuit consists of a divider-by-8 prescaler with its own preamplifier and at 5-bit programmable divider controlled by a serially-loaded data register. Four open-collector outputs, each independently programmable, are included. The device has two modes of operation, selected by the “mode select” input. In mode 1, the comparison frequency is 7.8125kHz and the programmable divider MSB is bypassed; mode 2 comparison frequency is 3.906.

SP503 : The SP503 is a highly integrated serial transceiver that allows software control of its interface modes. It offers hardware interface modes for RS-232 (V.28), RS-422A (V.11), RS-449, RS-485, V.35, and EIA-530. The SP503 is fabricated using low–power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Drivers Receivers SP503 Charge Pump Driver Decode Receiver Decode Date: 7/29/04 SP503 Multiprotocol Transceiver © Copyright 2004 Sipex Corporation 1 RR(b) 36 RT(b) 38 GND 29 C1– 30 C2– 31 GND 34 IC(b) 40 RI 21 ST 22 LL 24 VCC 25 C1+ 26 VDD 27 C2+ 28 VCC 33 VSS 32 ELECTRICAL CHARACTERISTICS TMIN to TMAX @ Vcc = +5V .

SP504 : SP504 WAN Multi-Mode Serial Transceiver • +5V Only • Seven (7) Drivers and Seven (7) Receivers • Driver and Receiver Tri-State Control • Reduced V.35 Termination Network • Pin Compatible with the SP503 • Software Selectable Interface Modes: -RS-232E (V.28) -RS-422A (V.11, X.21) -RS-449 (V.11 & V.10) -RS-485 -V.35 -EIA-530 (V.11 & V.10) -EIA-530A (V.11 & V.10) RxD 1 RDEC0 2 RDEC1 3 RDEC2 4 RDEC3 5 TTEN 6 SCTEN 7 N/C 8 TDEC3 9 TDEC2 10 TDEC1 11 TDEC0 12 DTR 13 TxD 14 TxC 15 RTS 16 RL 17 V35_STAT 18 DCD 19 RxC 20 -V.36 SP504 80 CTS 79 SCT 78 DSR 77 SCT(b) 76 SCT(a) 75 GND 74 VCC 73 VCC 72 GND 71 RD(b) 70 RD(a) 69 DM(b) 68 DM(a) 67 CS(b) 66 CS(a) 65 TT(b) 64 GND 63 T.