PLL500-17 Low Phase Noise VCXO (17MHz to 36MHz) FEATURES • • • • • • • • • • VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.
328MHz).
CMOS output with OE tri-state control.
17 to 36MHz fundamental crystal input.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.
5ps period jitter.
2.
5 to 3.
3V operation.
Available in 8-Pin SOIC, 6-pin SOT23 packages, or DIE.
BLOCK DIAGRAM PIN CONFIGURATION XIN VDD* VIN GND 1 2 3 4 8 7 6 5 XOUT OE^ VDD* CLK ^: Denotes internal Pull-up *: Only one VDD pin needs to be connected PLL500-17 DESCRIPTION The PLL500-17 is a low co...

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