128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 Revision History No.
0.
1 History 1) Defined Target Spec.
1) Added Pin Capacitance Spec.
& IDD Spec.
2) Corrected SPD typo(byte #22,#42) Corrected Pin assignment table Draft Date Feb.
2004 Apr.
2004 July 2004 Remark 0.
2 This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
2 / July 2004 1 128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 DESCRIPTION Hynix HYMP512R72(L)4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) whic...

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