DS1004 5-Tap High Speed Silicon Delay Line www.
dalsemi.
com FEATURES All-silicon timing circuit Five equally delayed clock phases per input Precise tap-to-tap delay tolerances of ±0.
5, ±0.
75, or ±1 ns Input-to-tap 1 delay of 5 ns Delay tolerances of ±1.
5 ns over temperature and voltage Leading and trailing edge precision preserves the input symmetry CMOS design with TTL compatibility Standard 8-pin DIP and 150 mil 8-pin SOIC Vapor phase, IR and wave solderable Available in Tape and Reel PIN ASSIGNMENT IN TAP 2 TAP 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004M 8-Pin DIP (300-mil) See Mech.
Drawings Section IN TAP 2 TAP 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-Pin SOIC (1...

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