ispClock 5500 Family ™ In-System Programmable Clock Generator with Universal Fan-Out Buffer August 2004 Data Sheet Features ■ ■ ■ ■ 10MHz to 320MHz Input/Output Operation Low Output to Output Skew (50ps) Low Jitter Peak-to-Peak(70ps) Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL • Programmable precision output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.
5V, 1.
8V, 2.
5V, 3.
3V • Programmable lock detect • Multiply and divide ratio controlled by - Input divider (5 bits) - Internal feedback divider (5 bits) - Five output divider...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)