KM48S8030D CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.
0 May 1999 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
0 May 1999 KM48S8030D Revision History Revision 0.
0 (May 15, 1999) CMOS SDRAM • Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.
PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice IIL IIL IOL Before Input leakage current (inputs) Input leakage current (I/O pins) Output open @ DC characteri...

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