MPC992

MPC990 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock driver. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC990/991 makes the device ideal for Workstation, Mainframe Computer and Telecommunication applications. The MPC990 and MPC991 devices are identical except in the interface to the reference clock for the PLL. The MPC990 offers an on–board crystal oscillator as the PLL reference while the MPC991 offers a differential ECL/PECL input for applications which need to lock to an existing clock signal. Both designs offer a secondary single–ended ECL clock for sy.

MPC993 : Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs Differential 2x output pairs Indicates detection of a bad input referen.

MPC9990 : Differential clock frequency input Differential feedback input Bank A outputs Bank B outputs Synchronization output Differential feedback output pull-down pull-down pull-down pull-down pull-up pull-up Selection of operating frequency range Selection of bank A output frequency Selection of bank B output frequency Selection of PLL operation or TEST mode (PLL bypass) Master reset. Assertion of master reset required on startup Output enable Analog power supply, typical 3.3 V Core power supply, typical 3.3 V Output power supply, typical 1.8 V Output, analog and core logic ground, 0V (VEE) VCC QA3 QA3 QA4 QA4 QA5 QA5 QA6 27 GND QA6 26 CLK 36 QA2 QA2 VCCO QA1 QA1 QA0 QA0 VCCO QSYNC QSYNC GND VCCA .

MPC9992 : FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range. The SYNC pulse gener.

MPC99J93 : The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section). PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 ÷2 PLL 200 -- 360 MHz ÷4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 Figure 1..