Preliminary Technical Data FEATURES 100 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 30 MHz and 31 MHz 81.6 dB SNR with 30 MHz input (3.2 V p-p input, 80Msps) 90 dBc SFDR with30 MHz input (3.2 V p-p input, 80Msps) Excellent linearity DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.3 W power dissipation 3.3 V and 5 V supply operation 2.0 V p-p to 3.2 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos compliment) Output clock available 16-Bit, 80/100 MSPS, A/D Converter AD9446 FUNCTIONAL BLOCK DIAGRAM AGND AVDD1 AVDD2 DRGND DRVDD DFS DCS MODE OUTPUT MODE AD9446 VIN+ VINBUFFER T/H PIPELINE ADC 16 OR LV...

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