Part Number
|
XCR5064 |
Manufacturer
|
Xilinx |
Description
|
64 Macrocell CPLD with Enhanced Clocking |
Published
|
Dec 28, 2005 |
Detailed Description
|
APPLICATION NOTE
0
R
XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
0 14*
DS044 (v1.1) February 10, 2000
Product...
|
Datasheet
|
XCR5064
|
Overview
APPLICATION NOTE
0
R
XCR5064C: 64 Macrocell CPLD with Enhanced Clocking
0 14*
DS044 (v1.
1) February 10, 2000
Product Specification speed and zero power in a 64 macrocell CPLD.
With the FZP design technique, the XCR5064C offers true pin-to-pin speeds of 7.
5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for `turbo bits' or other power down schemes.
By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLDz.
These devices are the first TotalCMOS PL...
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