Part Number
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CY7C1231F |
Manufacturer
|
Cypress Semiconductor |
Description
|
2Mbit Flow-Through SRAM |
Published
|
Jan 4, 2006 |
Detailed Description
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Features
• Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock
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Datasheet
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CY7C1231F
|
Overview
Features
• Can support up to 117-MHz bus operations with zero wait states — Data is transferred on every clock
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• Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 18 common I/O architecture • Single 3.
3V power supply • Fast clock-to-output times — 7.
5 ns (for 117-MHz device) — 8.
5 ns (for 100-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP package • Low standby power • Burst Capability—linear or interleaved burst order
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