| Part Number | HY5DU56822T |
| Manufacturer | Hynix Semiconductor |
| Title | (HY5DU56xxx(L)T) 2nd 256M DDR SDRAM |
| Description | and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent lice... |
| Features |
• • • • • • • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes... |
| File Size | 370.15KB |
| Datasheet |
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HY5DU56822AT : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV) 4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA 3. Revision 0.4 (May. 02) 1) Added comment of Cas Latrency 1.5 & 3 et4U.com DataSheet4U.
HY5DU56822BT-D4 : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Revision History 1. Revision 0.2 (Jan. 2003) 1) Changed VDDmin from 2.4V to 2.5V at Page22 2) Corrected some typos. 2. Revision 0.3 (Feb. 2003) 1) IDD value update at Page 23, 24. 2) Changed some AC Paramters on AC Characteristics Table at Page27, 28. 3. Revision 0.4 (Aug. 2003) 1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD) Rev. 0.4 / Aug. 2003 2 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU5642.
HY5DU56822BT-D43 : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Revision History 1. Revision 0.2 (Jan. 2003) 1) Changed VDDmin from 2.4V to 2.5V at Page22 2) Corrected some typos. 2. Revision 0.3 (Feb. 2003) 1) IDD value update at Page 23, 24. 2) Changed some AC Paramters on AC Characteristics Table at Page27, 28. 3. Revision 0.4 (Aug. 2003) 1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD) Rev. 0.4 / Aug. 2003 2 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU5642.
HY5DU56822CF : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ Nov. 2003 1 w w w .D at h S a t e e 4U . m o c HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F Revision History Revision No. 0.1 History Define Preliminary Specification Draft Date Nov. 2003 Remark Rev. 0.1 / Nov. 2003 2 HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F DESCRIPTION PRELIMINARY The Hynix HY5DU56422 and HY5DU56822 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256.
HY5DU56822CT : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edg.
HY5DU56822DT : and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1 www.DataSheet4U.com HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T Revision History Revision No. History First Version ReleaseMerged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Draft Date Remark 1.0 Oct. 2004 Rev. 1.0 /Oct. 2004 2 www.DataSheet4U.com HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T DESCRIPTION The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory a.
HY5DU56822DTP : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 /May 2004 www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION PRELIMINARY The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising e.
HY5DU56822E : and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /June. 2006 1 www.DataSheet4U.com HY5DU56822E(L)TP HY5DU561622E(L)TP 1 Revision History Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark Rev. 1.1 /June. 2006 2 www.DataSheet4U.com HY5DU56822E(L)TP HY5DU561622E(L)TP 1 DESCRIPTION The HY5DU56822E(L)TP and HY5DU561622E(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density a.
HY5DU56822EFP : and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / June 2006 1 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 Revision History Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark Rev. 1.1 / June 2006 2 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 DESCRIPTION The HY5DU56822E(L)FP, and HY5DU561622E(L)FP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR S.
HY5DU56822ELFP : and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / June 2006 1 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 Revision History Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark Rev. 1.1 / June 2006 2 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 DESCRIPTION The HY5DU56822E(L)FP, and HY5DU561622E(L)FP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR S.
HY5DU56822LT : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV) 4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA 3. Revision 0.4 (May. 02) 1) Added comment of Cas Latrency 1.5 & 3 et4U.com DataSheet4U.
HY5DU56822LT : and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1 www.DataSheet4U.com HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T Revision History Revision No. History First Version ReleaseMerged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Draft Date Remark 1.0 Oct. 2004 Rev. 1.0 /Oct. 2004 2 www.DataSheet4U.com HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T DESCRIPTION The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory a.
HY5DU56822LTP : and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 /May 2004 www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION PRELIMINARY The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising e.