MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2105C/D 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.
The MPC2105C and MPC2106C utilize synchronous BurstRAMs.
The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format.
The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3 V 64K x 18.
For tag bits, a 5 V cache tag RAM config...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)