• Pin/Software compatible with earlier V96BMC.
• Direct interfaces to i960Cx/Hx/Jx processors.
w w w .
D • 3.
3V DRAM interface support.
• Near SRAM performance achieved with DRAM.
• Supports up to 512Mb of DRAM.
• Interleaved or non-interleaved operation.
• Supports symmetric and non-symmetric arrays.
a ta Sh t e e 4U .
m V96BMC Rev.
D o c HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx® PROCESSORS • Software-configured operational parameters.
• Integrated Page Cache Management.
• 2Kbyte burst transaction support.
• On chip memory address multiplexer/drivers.
• Two 24-bit timers, 8-bit bus watch timer.
• Up to 40MHz operation.
• Low cost 132-pin PQFP package.
The V96BMC...

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