DATA SHEET 512M bits DDR2 SDRAM EDE5104AESK (128M words × 4 bits) EDE5108AESK (64M words × 8 bits) Description The EDE5104AESK is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108AESK is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 60-ball FBGA (µBGA) package.
Features • Power supply: VDD, VDDQ = 1.
8V ± 0.
1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential cloc...

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