( DataSheet : www.
DataSheet4U.
com ) PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AKTA-5 (32M words × 8 bits, DDR400) Description The EDD2508AKTA-5 is a 256M bits DDR SDRAM organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Pin Configurations /xxx indicates active low signal.
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