74LCX32

74LCX32 : The LCX32 contains four 2-input OR gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX32 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Information Package Order Number Number Package Description 74LCX32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX32SJ 74LC32BQX(1) M14D MLP14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74LCX32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC M.

74LCX32 : Pin Names An, Bn On DAP 1. DAP (Die Attach Pad) Description Inputs Outputs No Connect (Top View) (Bottom View) Figure 2. Pad Assignments for DQFN ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating VCC Supply Voltage –0.5 V to +7.0 V VI DC Input Voltage –0.5 V to +7.0 V VO DC Output Voltage, Output in HIGH or LOW State (Note 2) –0.5 V to VCC + 0.5 V IIK DC Input Diode Current, VI GND –50 mA IOK DC Output Diode Current VO GND –50 mA VO VCC +50 mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature –65°C to +150°C Stresses exceeding those listed in the .

74LCX32244 : The LCX32244 contains thirty-two non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 32-bit operation. The LCX32244 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 4.5 ns tPD max (VCC = 3.

74LCX32245 : The LCX32245 contains thirty-two non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LCX32245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Featur.

74LCX32373 : The LCX32373 contains thirty-two non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The LCX32373 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features I.

74LCX32374 : The LCX32374 contains thirty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 32-bit operation. The LCX32374 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features I 5V tolerant inputs and outputs I 2.3V–3.6V VCC specifications provided I 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max I Power down h.

74LCX32500 : These 36-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LCX32500 is designed for low voltage (2.5V or 3.3V) VCC applications with the capability of interfacing to a 5V signal environment. The LCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power down high im.

74LCX32646 : The LCX32646 contains thirty-two non-inverting bidirectional registered bus transceivers with 3-STATE outputs, providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 32-bit operation.The DIRn inputs determine the direction of data flow through the device. The CPABn and CPBAn inputs load data into the registers on the LOW-toHIGH transition (see Functional Description). The LCX32646 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32646 is fabricated with an advanced CMOS technology to a.

74LCX32652 : The LCX32652 contains thirty-two non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Each byte has separate control inputs which can be shorted together for full 32-bit operation. Output Enable pins (OEABn, OEBAn) are provided to control the transceiver function (see Functional Description). The LCX32652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32652 is fabricated with an advanc.

74LCX373 : The LCX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage applications with capability of interfacing to a 5V signal environment. The LCX373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Information Order Number Package Number Package Description 74LCX373WM 74LCX373SJ 74LCX373BQX(2) M20B M20D MLP20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5.

74LCX374 : The 74LCX374 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance sta.

74LCX374 : The LCX374 consists of eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered clock (CP) and Output Enable (OE) are common to all flip-flops. The LCX374 is designed for low-voltage (3.3V or 2.5V) VCC applications with capability of interfacing to a 5V signal environment. The LCX374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 8.5 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power-down high impedance inputs and outputs s Supports live insertion/withdraw.

74LCX374 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low-Voltage CMOS Octal D-Type Flip-Flop With 5V-Tolerant Inputs and Outputs (3-State, Non-Inverting) The MC74LCX374 is a high performance, non–inverting octal D–type flip–flop operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX374 inputs to be safely driven from 5V devices. The MC74LCX374 consists of 8 edge–triggered flip–flops with individual D–type inputs and 3–state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip–flops. Th.

74LCX374 : MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low-Voltage CMOS Octal D-Type Flip-Flop With 5V-Tolerant Inputs and Outputs (3-State, Non-Inverting) The MC74LCX374 is a high performance, non–inverting octal D–type flip–flop operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX374 inputs to be safely driven from 5V devices. The MC74LCX374 consists of 8 edge–triggered flip–flops with individual D–type inputs and 3–state true outputs. The buffered clock and buffered Output Enable (OE) are common to all flip–flops. Th.

74LCX374 : .

74LCX38 : The LCX38 contains four 2-input open drain NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX38 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs s 2.3V–3.6V VCC specifications provided s 6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s ±24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model 2000V Machine model 150V Ordering Code: Order Number 74LCX38M 74LCX38SJ 74LCX38MTC Package N.