SY16

SY10 : The SY10 synchronization module is a Digital PLL (DPLL), which utilizes application specific software in the digital signal processor (DSP). The DSP is complemented by fast hardware logic (FPGA) where all multiplexers, counters, dividers, phase detectors, output frequency converters and other control logic circuits are completely implemented. The functional block diagram with maximum configuration is shown in figure 1. The module has three phase lock loop – primary PLL, secondary and utility PLL. The primary PLL utilizes a Direct Digital Synthesis (DDS) technique combined with a high stability OCXO in order to provide an accurate and fast DPLL response and eliminates the requirement for an .

SY10-100EP451L : The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have an internal 75kΩ pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to a value smaller than VEE +1.2V, the clamp will override and force the output to a default state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. Datasheets and support docu.

SY100 : 3 Port Solenoid Valve Rubber Seal Series SY100 1 Low power consumption: 0.5 W (Standard, Without indicator light) (Current draw: 21 mA at 24 VDC) V100 ∗ Large flow type: 0.75 W (Current draw: 31 mA at 24 VDC) [Energy saving type [0.22 W] is available, too. For details, refer to catalog on page 4-3-15.] [Low wattage [0.45 W] is available, too. For details, refer to catalog on page 4-3-15.] Body width: 10 mm Effective area 0.14 mm2 (Standard type) Effective area 0.22 mm2 (Large flow type) SY SYJ VK High reliability 100 million cycles or more (By SMC life test data) VZ VT VP VG VP S070 VQ VKF Available in vacuum applications (Up to –100 kPa) VQZ VZ VS Copper-free VFN No copp.

SY100E016 : The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture and operation are the same as the Motorola MC10H016 in the MECL 10KH family, extended to 8 bits, as shown in the logic diagram. The counters feature internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW, the TC feedback is disabled and counting proceeds continuously, with TC going LOW to indicate an all-HlGH state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. PIN NAMES Pin P0-P7 Q0-Q7 CE PE MR CLK TC TCLD VC.

SY100E101 : The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems. The E101 features both true and complementary outputs. BLOCK DIAGRAM PIN NAMES Pin Dna, Dnb, Dnc, Dnd Q0-Q3 Q0-Q3 VCCO Function Data Inputs True Outputs Inverting Outputs VCC to Output M9999-032006 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: G Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10E101 SY100E101 PACKAGE/ORDERING INFORMATION 28-Pin PLCC (J28-1) Ordering Information(1) Part Number SY10E101JI SY10E101JITR(2) SY100E101JI SY100E101JITR(2) SY10E101JC SY10E101JCTR(2) SY100E101JC SY100E101JCTR(2) SY10E101JY(3) Package Operating Type Range J28-1 Industrial J28-1 Indu.

SY100E104 : The SY10/100E104 are quint 2-input AND/NAND gates designed for use in new, high-performance ECL systems. The E104 also features a function output, F, which is the OR of all five AND gate outputs, while F is the NOR. Both true and complementary outputs are provided. BLOCK DIAGRAM D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b PIN NAMES F Pin Function Dna, Dnb Data Inputs F Q0-Q4 AND Outputs Q0-Q4 NAND Outputs Q0 F OR Output Q0 F NOR Output VCCO VCC to Output Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 M9999-032006 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: H Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10E104 SY100E104 PACKAGE/ORDERING INFORMATION 28-Pin PLCC (J28-1) Ordering Info.

SY100E107 : The SY10/100E107 offer five 2-input XOR/XNOR gates and are designed for use in new, high- performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and complementary outputs are provided. BLOCK DIAGRAM D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b PIN NAMES F Pin Function Dna, Dnb Data Inputs F Q0-Q4 Q0-Q4 Q0 F XOR Outputs XNOR Outputs OR Output Q0 F VCCO NOR Output VCC to Output Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 M9999-032006 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: F Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10E107 SY100E107 PACKAGE/ORDERING INFORMATION Ordering Information(1) D3a D4.

SY100E111 : The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all /Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to .

SY100E111A : The SY10/100E111A/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/100E111A/L's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either differential or singleended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The E111A/L are specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent .

SY100E111AL : The SY10/100E111A/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/100E111A/L's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either differential or singleended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The E111A/L are specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent .

SY100E112 : The SY10/100E112 are quad drivers designed for use in new, high-performance ECL systems. The E112 has two pairs of OR/NOR outputs from each gate and a common, buffered enable input. The data input can also be used as an ECL memory address fan-out driver, although the E111 is designed specifically for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the SY10/100E212 device. BLOCK DIAGRAM D0 D1 D2 D3 EN PIN NAMES Pin Q0a Q0b D0-D3 Q0a EN Q0b Qna, Qnb Qna, Qnb Q1a VCCO Q1b Q1a Q1b Q2a Q2b Q2a Q2b Q3a Q3b Q3a Q3b Function Data Inputs Enable Input True Outputs Inverting Outputs VCC to Output M9999-0.

SY100E116 : The SY10/100E116 are quint differential line receivers designed for use in new, high-performance ECL systems. These devices have emitter-follower outputs and an internally generated reference supply (VBB) for singleended reception. Active current sources combined with Micrel’s ASSET™ technology provide the receivers with excellent common mode noise rejection. The receiver design features clamp circuitry to cause a defined output state if both the inverting and non-inverting inputs are left open; in this case the Q output goes LOW, while the Q output goes HIGH. If both inverting and non-inverting inputs are at equal potential, the receiver does not go to a defined state, but rather shares cur.

SY100E122 : The SY10/100E122 are 9-bit buffers designed for use in new, high-performance ECL systems. The E122 provides nine non-inverting buffers. BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 PIN NAMES Pin D0-D8 Q0-Q8 VCCO Function Data Inputs Data Outputs VCC to Output M9999-032006 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: G Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10E122 SY100E122 PACKAGE/ORDERING INFORMATION Ordering Information(1) D8 NC NC NC NC Q8 VCCO D7 D6 D5 VEE D4 D3 D2 25 24 23 22 21 20 19 26 18 27 17 28 PLCC 16 1 TOP VIEW 15 2 J28-1 14 3 13 4 12 5 6 7 8 9 10 11 Q7 Q6 VCC Q5 Q4 VCCO Q3 D1 D0 NC Q0 Q1 VCCO Q2 28-Pin PLCC (J28-.

SY100E131 : The SY10/100E131 are high-speed quad master slave D-type flip-flops with differential outputs designed for use in new, high-performance ECL systems. The flip-flops may be individually clocked by holding CC (Common Clock) at a logic LOW and then using the four individual CE (Clock Enable CE0–CE3) inputs to accomplish such clocking. Alternatively, all four flip-flops can be clocked in common by holding the CE inputs LOW and then using CC to clock the data. In the common clock mode, the CE input acts as a control that passes the CC signal to the flip-flop. Data is clocked into the flip-flop on the rising edge of the output of the logical OR operation between CE and CC (data enters the master wh.

SY100E136 : The SY10/100E136 are 6-bit synchronous, presettable, cascadable universal counters. These devices generate a look-ahead-carry output and accept a look-ahead-carry input. These two features allow for the cascading of multiple E136s for wider bit width counters that operate at very nearly the same frequency as the stand-alone counter. The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. For more information on utilizing the look-ahead-carry features of the device, please refer to the applications section of this data sheet. The differential COUT output fa.

SY100E137 : The SY10/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLinPS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level. The devices are ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous ena.

SY100E141 : The SY10/100E141 are 8-bit, full-function shift registers designed for use in new, high-performance ECL systems. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0–D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The two select pins, SEL0 and SEL1 permit four modes of operation: Load, Hold, Shift Left and Shift Right, as shown in the Truth Table. Input data is clocked into the register on the rising clock edge after meeting the minimum set-up time. A logic HIGH on the Master Reset (MR) pin asynchronously resets all the registers to zero. PIN NAMES Pin D0-D7 DL, DR SEL0, SEL1 CLK Q0-Q7 M.