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com CY7C1223F 2-Mb (128K x 18) Pipelined DCD Sync SRAM Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K × 18-bit common I/O architecture • 3.
3V –5% and +10% core power supply (VDD) • 3.
3V I/O supply (VDDQ) • Fast clock-to-output time — 3.
5 ns (for 166-MHz device) — 4.
0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100-...

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