com Features General • High-performance, Low-power AVR® (AVR3 Core) Enhanced RISC Architecture • • • • • • – 133 Powerful Instructions (Most Executed in a Single Clock Cycle) Low-power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 6000V Operating Range: from 2.
7V to 5.
5V Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible Available in Wafers, Modules and Industry-standard Packages Memory • 192K Bytes of ROM Program Memory • 64K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Bytes – 1 to 128-byte Program/Erase – 2 ms Program, 2 ms Erase – Typically More than 300,000 Write/Erase Cycles...

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