com Features General • • • • • • • High-performance, Low-power secureAVR RISC Architecture – 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 6000V Operating Ranges: 1.
62 to 5.
5V Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible Available in Wafers, Modules, and Industry-standard Packages Memory • 192K Bytes of ROM Program Memory • 36K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area – 1 to 128-byte Program / Erase – 1 ms Program / 1 ms Erase – Typically More than 500,000 Write/Erase Cycles at a Temperatur...

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