com EP520 SDRAM Controller December 5, 2000 Product Specification AllianceCORE™ Facts Core Specifics Supported Family Virtex Device Tested V50-6 CLB Slices 287 1 Clock IOBs1 IOBs1 116 Performance (MHz) 91 Xilinx Tools 3.
2i Special Features None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.
ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used Model Technology Modelsim™ 5.
4b Support Support provided by Eureka Technology Notes: 1.
Assuming all core I/Os are routed off-chip Eureka Technology, Inc.
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