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S amHop Microelectronics C orp.
S T U/D3030NLS
F E AT UR E S
( mW)
Aug 08 , 2005
N-C hannel Logic Level E nhancement Mode Field E ffect
Transistor
P R ODUC T S UMMAR Y
V DS S
30V
ID
30A
R DS (ON)
Max
S uper high dense cell design for low R DS (ON ).
18 @ V G S = 10V 25 @ V G S = 4.
5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
D G S
G D
S
G
S TU S E R IE S TO-252AA(D-P AK)
S TD S E R IE S TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (Ta=25 C unless otherwise noted)
P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a -P ulsed @ Tc=25 C S ymbol V DS V GS ID IDM IS PD T J , T S TG Limit 30 20 30 75 20 50 -55 to 175 Unit V...