White Electronic Designs 32Mx72 REGISTERED DDR SDRAM FEATURES „ „ „ „ „ „ „ „ „ Registered for enhanced performance of bus speeds of 200, 250, 266Mb/s Package: • 208 Plastic Ball Grid Array (PBGA), 16 x 25mm 2.
5V ±0.
2V core power supply 2.
5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.
e.
, source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions ...

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