PRELIMINARY 256Mb: x32 SDRAM SYNCHRONOUS DRAM FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can www.
DataSheet4U.
com be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh (15.
6µs/row) • LVTTL-compatible inputs and outputs • Single +3.
3V ±0.
3V power supply • Supports CAS latency of 1, 2, and 3 MT48LC8M32B2 - 2 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron W...

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