CY29352 2.
5V or 3.
3V, 200 MHz, 11 Output Zero Delay Buffer Features ■ ■ ■ ■ Description The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.
The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs.
Bank A divides the VCO output by four and six while bank B divides by four and two, and bank C divides by two and four per SEL(A:C) settings, see Table 3 on page 3.
These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3.
Each LVCMOS compatible output drives 50Ω series or parallel terminated transmission ...

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