IDTTM InterpriseTM Integrated Communications Processor 79RC32334—Rev.
Y RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture (ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions – Supports big or little endian operation com – MMU with 32 page TLB – 8kB Instruction Cache, 2-way set associative – 2kB Data Cache, 2-way set associative – Cache locking per line – Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management – Compatible with a wide variety of operating systems ◆ Local Bus Interface – Up to 7...

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