DFPCOMP com Floating Point Comparator Unit ver 2.
10 OVERVIEW DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ The DFPCOMP compares two arguments.
The input numbers format is according to IEEE-754 standard.
DFPCOMP supports single precision real numbers.
Compare operation was pipelined up to 1 level.
Input data are fed every clock cycle.
The first result appears after 1 clock period latency and ...

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