DFPSQRT com Floating Point Pipelined Square Root Unit ver 2.
90 OVERVIEW ♦ Fully synthesizable, static synchronous design with no internal tri-states The DFPSQRT uses the pipelined mathematics algorithm to compute square root function.
The input number format is according to IEEE-754 standard.
DFPSQRT supports single precision real numbers.
SQRT operation can be pipelined up to 9 levels.
Input data are fed every clock cycle.
The first result appears after 9 clock periods latency and next results are available each clock cycle.
Precision and accuracy are parameterized.
DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDI...

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