December 2004 ® AS7C251MNTF18A 2.
5V 1M x 18 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.
5/8.
5/10 ns Fast OE access time: 3.
5/4.
0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Clock enable for operation hold Multiple chip enables for easy expansion 2.
5V core power supply Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation com Logic block diagram A[19:0] 20 D Address register b...

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