February 2005 ® AS7C251MPFD32A AS7C251MPFD36A 2.
5V 1M × 32/36 pipelined burst synchronous SRAM Features • Organization: 1,048,576 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.
1/3.
5/3.
8 ns • Fast OE access time: 3.
1/3.
5/3.
8 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.
DataSheet4U.
com • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 2.
5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs Logic block diagram LBO CLK ADV ADSC AD...

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